The present invention relates to concurrent logic operations using decoder circuitry of a look-up table.
A field programmable gate array (FPGA) includes lookup tables (LUTs), which can be programmed to implement different functions. Lookup tables are used to implement functions of xe2x80x98nxe2x80x99 inputs, where xe2x80x98nxe2x80x99 depends on the size of lookup table and the addressing scheme involved. The lookup table is most efficiently used when its number of inputs are fully utilized, and there are many combinations formed based upon the inputs. U.S. Pat. No. 6,037,829 describes an implementation for a lookup table decoder.
The Xilinx programmable logic data book (Feb. 16, 1999, Version 1.3, Pages 3-9) describes the Virtex architecture with a dedicated multiplier by adding a two input AND gate at two of the four inputs of the lookup table 4, as shown in FIG. 1. This is a dedicated multiplier, and is particularly useful while designing large multipliers. It is also useful in many other applications. The major disadvantage lies in the fact that a separate AND gate is fabricated with each LUT for achieving the AND gate functionality. A significant amount of chip area is used in fabricating the AND gates along with the lookup table.
An object of the present invention is to prevent the above described drawbacks by utilizing the decoder circuit gates of a look-up table for achieving the same functionality, and thereby eliminating the need for an additional AND gate.
Another object of the present invention is to reduce the additional circuitry required for generation of XOR/XNOR functions by using a single NOR gate.
These and other objects, features, and advantages in accordance with the present invention are provided by an improved look-up table (LUT) that includes address decoder circuitry comprising means or circuitry for utilizing the address decoder circuitry for producing secondary functions concurrently with the address decoding operations, thereby eliminating or reducing additional circuitry required for generating the secondary functions.
The means or circuitry is a selected output of the address decoder used to produce an AND function of two predetermined inputs of the decoder. The means may also be a NOR gate connected to two selected outputs of the address decoder for producing an EXCLUSIVE-OR or EXCLUSIVE-NOR function of two predetermined inputs to the decoder. The means may also be a programmable AND-NOR logic array for producing a sum-of-products/product-of-sums output from selected outputs of the address decoder.
The look-up table may be used in a configurable logic element. The present invention also provides a programmable logic device containing a plurality of configurable logic elements.
Another aspect of the present invention is to provide a method for eliminating or reducing the additional circuitry required for the generation of secondary functions. The method comprises utilizing the address decoder circuitry in the lookup table for producing the secondary functions concurrently with the address decoding operations.
The selected output of the address decoder is used to produce an AND function of two predetermined inputs of the decoder. A NOR gate may be connected to two selected outputs of the address decoder for producing an EXCLUSIVE-OR or EXCLUSIVE-NOR function of two predetermined inputs to the decoder. A programmable AND-NOR logic array may also be used for producing a sum-of-products/product-of-sums output from selected outputs of the address decoder.